SH7763 Datasheet, PDF (1496/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
Bit
6 to 4
3
2
1
0
Bit Name
CKDV
Initial
Value
All 0
MUEN
0

0
TRMD
0
EN
0
R/W
R/W
R/W
R
R/W
R/W
Description
Serial Oversampling Clock Division Ratio
These bits define the division ratio between
oversampling Clock (SSI_CLK) and the serial bit clock.
These bits are ignored if SCKD = 0.
The Serial Bit Clock is used for the shift register and is
provided on the SSI_SCK pin.
000: (Serial bit clock frequency = oversampling clock frequency/1)
001: (Serial bit clock frequency = oversampling clock frequency/2)
010: (Serial bit clock frequency = oversampling clock frequency/4)
011: (Serial bit clock frequency = oversampling clock frequency/8)
100: (Serial bit clock frequency = oversampling clock frequency/16)
101: (Serial bit clock frequency = oversampling clock frequency/6)
110: (Serial bit clock frequency = oversampling clock frequency/12)
111: Setting prohibited
Mute Enable
0: The SSI module is not muted
1: The SSI module is muted
Reserved
This bit is always read as 0. The write value should
always be 0.
Transmit/Receive Mode Select
0: The SSI module is in receive mode
1: The SSI module is in transmit mode
SSI Module Enable
0: The SSI module is disabled
1: The SSI module is enabled
Rev. 1.00 Oct. 01, 2007 Page 1430 of 1956
REJ09B0256-0100