SH7763 Datasheet, PDF (1013/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Bit
Initial
Bit
Name Value R/W Description
31
RACT 0
R/W Receive Descriptor Valid/Invalid
Indicates whether this descriptor is valid or invalid. To make
this bit valid, prepare a receive buffer (user-specified
receive data storage destination) beforehand, then write 1
to this bit. The E-DMAC clears this bit to 0 after data
transfer.
0: Indicates that this receive descriptor is invalid
Indicates the initial setting state, the state after 0 is
written to, or (in case the user writes 1 to this bit) that this
bit is cleared to 0 because the E-DMAC data transfer
processing is completed
If this state is recognized when the E-DMAC reads a
descriptor, the E-DMAC clears the RR bit in EDRRR to
0, and halts transfer operation related to reception by the
E-DMAC
1: Indicates that this receive descriptor is valid
Indicates that data is not transferred yet after the user
writes 1 to this bit, or that data is being transferred
When there is a descriptor row (descriptor list) consisting
of multiple continuous descriptors, the E-DMAC can
continue operation when this bit of the next descriptor is
valid
30
RDLE 0
R/W Receive Descriptor List End
Indicates whether this descriptor is the last descriptor of the
descriptor row (descriptor list).
0: Not last descriptor
After transfer of this descriptor, the E-DMAC reads the
next one in the list of continuous descriptors
1: Last descriptor
After transfer of this descriptor, the E-DMAC reads the
descriptor placed at the address indicated by RDLAR
Rev. 1.00 Oct. 01, 2007 Page 947 of 1956
REJ09B0256-0100