SH7763 Datasheet, PDF (1359/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
Initial
Bit
Bit Name Value R/W Description
2
TY2
0
R/W Specifies open-ended multiblock transfer.
Bits TY1 and TY0 should be set to 01 or 10.
The command sequence of the multiblock transfer
specified by this bit ends when it is aborted by the
CMD12 command.
1, 0
TY[1:0]
0
R/W These bits specify the existence and direction of
transfer data.
00: A command without data transfer
01: A command with read data reception
10: A command with write data transmission
11: Set this bit when transmitting Stop Tran
Table 31.4 summarizes the correspondence between the commands described in the
MultiMediaCard System Specification Version 3.1 and the settings of the CMDTYR and
RSPTYR registers.
31.3.2 Response Type Register (RSPTYR)
RSPTYR specifies the command format in conjunction with CMDTYR. The bits RTY[2:0]
specify the number of response bytes, and the bits RTY5 and RTY4 specify the additional settings.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
— RTY5 RTY4 —
RTY[2:0]
0
0
0
0
0
0
0
R R/W R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7, 6

All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
RTY5
0
R/W Set this bit when using a command with an R1b
response
Rev. 1.00 Oct. 01, 2007 Page 1293 of 1956
REJ09B0256-0100