SH7763 Datasheet, PDF (1070/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
Initial
Bit
Bit Name Value
15
CKSL
0
14

0
13, 12 CKDV[1:0] 00
11 to 9 
All 0
8
REQEN 0
R/W Description
R/W Operating Clock
Selects the source clock for the stream data transfer
clock
0: Peripheral clock 0 is used as the stream data
transfer clock (stream data transfer clock is output
from the ST_CLK pin)
1: External input clock is used as the stream data
transfer clock (stream data transfer clock is input
from the ST_CLK pin)
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Operating Clock Division Ratio
These bits specify the division ratio when peripheral
clock 0 is selected as the stream data transfer clock.
00: Stream data transfer clock is 1/2 of peripheral
clock 0
01: Stream data transfer clock is 1/4 of peripheral
clock 0
10: Stream data transfer clock is 1/8 of peripheral
clock 0
11: Setting prohibited
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W ST_REQ Pin Enable
Selects whether or not to use the ST_REQ pin.
0: ST_REQ pin is not used
1: ST_REQ pin is used
(1) At reception: ST_REQ is output when the free
space in FIFO is 8 bytes or less
(2) At transmission: Transmission is stopped when
ST_REQ is input
Rev. 1.00 Oct. 01, 2007 Page 1004 of 1956
REJ09B0256-0100