SH7763 Datasheet, PDF (1518/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
34.4.5 Receive Operation
As with transmission the reception can be controlled in one of two ways: either DMA or an
interrupt driven.
Figures 34.21 and 34.22 show the flow of operation.
When disabling the SSI module, the SSI clock must be supplied continuously until the module
enters in the idle state, which is indicated by the IIRQ bit.
Note: * SCKD = 0: Clock input through the SSI_SCK pin
SCKD = 1: Clock input through the SSI_CLK pin
Rev. 1.00 Oct. 01, 2007 Page 1452 of 1956
REJ09B0256-0100