SH7763 Datasheet, PDF (1473/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Audio Codec Interface (HAC)
Initial
Bit
Bit Name Value R/W Description
13
PLRFOV 0
R/W PCML RX Overrun
0: No PCML RX data overrun has occurred.
1: PCML RX data overrun has occurred because the
HAC has received new data from slot 3 before PCML
data is not read out.
12
PRRFOV 0
R/W PCMR RX Overrun
0: No PCMR RX data overrun has occurred.
1: PCMR RX data overrun has occurred because the
HAC has received new data from slot 4 before
PCMR data is not read out.
11 to 0 
All 0 R
Reserved
Always 0 for read and write.
Note: * This register is read/write. Writing 0 to the bit initializes it but writing 1 has no effect.
33.3.10 HAC Control Register (HACACR)
HACACR is a 32-bit read/write register used for controlling the HAC interface.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− − DMA DMA
RX16 TX16
− − TX12_
ATOMIC
RXD
MAL_
EN
TXD
MAL_
EN
RXD
MAR_
EN
TXD
MAR_
EN
−
−
−−−
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
R R/W R/W R R R/W R R/W R/W R/W R/W R R R R R
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
−− − −− −− − − − − −− − − −
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Initial
Bit
Bit Name Value R/W Description
31

1
R
Reserved
Always 1 for read and write..
30
DMARX16 0
R/W 16-bit RX DMA Enable
0: Disables 16-bit packed RX DMA mode. Enables the
RXDMAL_EN and RXDMAR_EN settings.
1: Enables 16-bit packed RX DMA mode. Disables the
RXDMAL_EN and RXDMAR_EN settings.
Rev. 1.00 Oct. 01, 2007 Page 1407 of 1956
REJ09B0256-0100