SH7763 Datasheet, PDF (696/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 15 External CPU Interface (EXCPU)
(3) Timing Charts of External CPU Access
External CPU access through the EXCPU is done through handshaking of the access request
(BREQ) and access acknowledge (BACK) signals.
Figures 15.2 and 15.3 show the access timing of the EXCPU and external CPU.
Read access
CLKOUT
BREQ
BACK
EX_CS0
EX_BS
EX_FRAME
EX_RDWR
EX_AD [31:0]
High
EX_RDY
Write access
CLKOUT
BREQ
BACK
EX_CS0
EX_BS
EX_FRAME
EX_RDWR
Low
EX_AD [31:0]
EX_RDY
A0
D0
A0
D0
Figure 15.2 External CPU Access (Single Access)
Rev. 1.00 Oct. 01, 2007 Page 630 of 1956
REJ09B0256-0100