SH7763 Datasheet, PDF (839/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 Realtime Clock (RTC)
Bit
7
6 to 5
4
3
2 to 1
Initial
Bit Name Value
R/W
CF
Undefined R/W
—
Undefined R
CIE
0
R/W
AIE
0
R/W
—
Undefined R
Description
Carry Flag
This flag is set to 1 on generation of a second counter
carry, or a 64 Hz counter carry when the 64 Hz counter
is read. The count register value read at this time is not
guaranteed, and so the count register must be read
again.
0: No second counter carry, or 64 Hz counter carry
when 64 Hz counter is read
[Clearing condition]
When 0 is written to CF
1: Second counter carry, or 64 Hz counter carry when
64 Hz counter is read
[Setting conditions]
Generation of a second counter carry, or a 64 Hz
counter carry when the 64 Hz counter is read
When 1 is written to CF
Reserved
The initial value of these bits is undefined. A write to
these bits is invalid, but the write value should always
be 0.
Carry Interrupt Enable Flag
Enables or disables interrupt generation when the carry
flag (CF) is set to 1.
0: Carry interrupt is not generated when CF flag is set
to 1
1: Carry interrupt is generated when CF flag is set to 1
Alarm Interrupt Enable Flag
Enables or disables interrupt generation when the
alarm flag (AF) is set to 1.
0: Alarm interrupt is not generated when AF flag is set
to 1
1: Alarm interrupt is generated when AF flag is set to 1
Reserved
The initial value of these bits is undefined. A write to
these bits is invalid, but the write value should always
be 0.
Rev. 1.00 Oct. 01, 2007 Page 773 of 1956
REJ09B0256-0100