SH7763 Datasheet, PDF (324/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value
31
IC00
0
30
IC01
0
29
IC02
0
28
IC03
0
27
IC04
0
26
IC05
0
25
IC06
0
24
IC07
0
23 to 0 —
All 0
R/W Description
R/W _{Clears masking of an}
independent interrupt
request of IRQ0.
R/W _{Clears masking of an}
independent interrupt
request of IRQ1.
R/W _{Clears masking of an}
independent interrupt
request of IRQ2.
R/W _{Clears masking of an}
independent interrupt
request of IRQ3.
[When reading]
An undefined value is
read.
[When writing]
0: Invalid
1: Clears the
corresponding interrupt
mask (Interrupts are
enabled)
R/W _{Clears masking of an}
independent interrupt
request of IRQ4.
R/W _{Clears masking of an}
independent interrupt
request of IRQ5.
R/W _{Clears masking of an}
independent interrupt
request of IRQ6.
R/W _{Clears masking of an}
independent interrupt
request of IRQ7.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 258 of 1956
REJ09B0256-0100