SH7763 Datasheet, PDF (1072/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
25.3.2 Control Registers 0, 1 (STICR0, STICR1)
STICR enables or disables the STIF module and sets the packet interval for stream data
transmission.
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− −− −
ICYC[11:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RTS − − − − − − − − − − − − − − EN
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R R R R R R R R R R R R/W
Bit
Bit Name
31 to 28 
Initial
Value
All 0
27 to 16 ICYC[11:0] All 0
15
RST
0
14 to 1 
All 0
0
EN
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Cycles between Transmit Packets
These bits set the fixed value when a fixed value is
used as the number of cycles between packets
during transmission. 1 to 4096 cycles of peripheral
clock 0 can be inserted as idle cycles between
packets.
R/W STIF Module Reset
Writing 1 to this bit resets the STIF module. This bit is
always read as 0.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W STIF Module Enable
0: STIF module is disabled
1: STIF module is enabled
Rev. 1.00 Oct. 01, 2007 Page 1006 of 1956
REJ09B0256-0100