SH7763 Datasheet, PDF (720/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 Watchdog Timer and Reset (WDT)
17.4 Operation
17.4.1 Reset request
Power-on reset and manual reset are available. These sources are follows.
(1) Power-on reset
1. Reset sources
• Input low level via PRESET pin.
• The WDTCNT overflows when the WT/IT bit in the WDTCSR is 1, and the RSTS bit is 0.
• The H-UDI reset occurs (For details, see section 42, User Debugging Interface (H-UDI)).
2. Branch destination address: H'A000 0000
3. Operation in branch
Exception code H'000 is set in the EXPEVT register. The VBR and SR registers are initialized,
and the program branches to PC =H'A000 0000. By initialization, the VBR register is set to
H'0000 0000. In the SR register, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0,
and the IMASK3 to IMASK0 bits (interrupt mask level) are set to B'1111.
The CPU and the peripheral modules are also initialized. For details, see the register descriptions
in each section.
When the power is turned on, be sure to input a low level to the PRESET pin. The TRST pin
should also be brought low level to initialize the H-UDI.
Power_on_reset()
{
EXPEVT = H'0000 0000;
VBR = H'0000 0000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(PowerOn);
PC = H'A000 0000;
}
Rev. 1.00 Oct. 01, 2007 Page 654 of 1956
REJ09B0256-0100