SH7763 Datasheet, PDF (372/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Program execution state
ICR0.MAI=1?
No
Yes
Yes
NMI input is low?
No
No
Interrupt
generated?
Yes
Yes
SR.BL = 0 or
Sleep mode?
No
No
ICR0.NMIB=1?
Yes
No
NMI?
Yes
No
NMI?
Yes
Level 15
No
interrupt?
Yes
Level 14
No
interrupt?
Yes _{SR. IMASK level}
is 14 or low
Yes
Level 1
No
No _{Yes SR. IMASK level}
is 14 or low
interrupt?
Yes
No _{Yes SR. IMASK level}
is 0?
No
No
CPUOPM.INTMU = 1?
Yes
Set SR. IMASK to
accepted interrupt level
Set interrupt source
code in INTEVT
Save SR to SSR;
save PC to SPC;
save R15 to SGR
Branch to
exception handing routine
Figure 9.4 Interrupt Operation Flowchart
Rev. 1.00 Oct. 01, 2007 Page 306 of 1956
REJ09B0256-0100