SH7763 Datasheet, PDF (339/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Function
Description
17
PCIC3 0
R
16
PCIC2 0
R
15
PCIC1 0
R
14
PCIC0 0
R
13
HAC
0
R
12
CMT
0
R
11 to 9 —
All 0
R
8
DMAC 0
R
7
H-UDI 0
R
6
—
0
R
5
WDT
0
R
4
SCIF1 0
R
3
SCIF0 0
R
2
RTC
0
R
Indicates PCIC3 interrupt source Indicates interrupt
Indicates PCIC2 interrupt source ^{sources for each}
peripheral module
Indicates PCIC1 interrupt source _{(INT2A1 is affected by}
Indicates PCIC0 interrupt source ^{the state of the}
interrupt mask
Indicates HAC interrupt source _register).
Indicates CMT interrupt source _{0: No interrupts}
These bits are always read as 0. _{1: Interrupts are}
The write value should always
generated
be 0.
Note: Reading the
Indicates DMAC interrupt source
INTEVT code
Indicates H-UDI interrupt source
This bit is always read as 0. The
write value should always be 0.
notified to the
CPU directly
can identify
interrupt
Indicates WDT interrupt source
sources. In this
Indicates SCIF1 interrupt source
Indicates SCIF0 interrupt source
case, reading
INT2A1 is not
necessary.
Indicates RTC interrupt source
1
TMU1 0
R
Indicates TMU1 interrupt source
0
TMU0 0
R
Indicates TMU0 interrupt source
Rev. 1.00 Oct. 01, 2007 Page 273 of 1956
REJ09B0256-0100