SH7763 Datasheet, PDF (148/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 4 Pipelining
(2-1) 1-step operation (EX type): 1 issue cycle
EXT[SU].[BW], MOVT, SWAP, XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#,
NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, CLRS, CLRT, SETS, SETT
Note: Except for AND#, OR#, TST#, and XOR# instructions using GBR relative
addressing mode
I1
I2
ID E1 E2 E3 WB
(2-2) 1-step operation (LS type): 1 issue cycle
MOVA
I1
I2
ID s1
s2
s3 WB
(2-3) 1-step operation (MT type): 1 issue cycle
MOV#, NOP
I1
I2
ID E1/S1 E2/s2 E3/s3 WB
(2-4) MOV (MT type): 1 issue cycle
MOV
I1
I2
ID E1/s1 E2/s2 E3/S3 WB
Figure 4.2 Instruction Execution Patterns (2)
Rev. 1.00 Oct. 01, 2007 Page 82 of 1956
REJ09B0256-0100