SH7763 Datasheet, PDF (392/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Area
External
addresses
Size
Specifiable
Connectable Memory Bus Width Access Size*⁷
2
H'0800 0000 to 64 Mbytes SRAM
H'0BFF FFFF
Burst ROM
8, 16, 32*²
8, 16, 32*²
8/16/32 bits
and 32 bytes
MPX
32*²
(DDR-SDRAM*⁴)
32
3*³
H'0C00 0000 to 64 Mbytes (DDR-SDRAM)
32
H'0FFF FFFF
8/16/32 bits
and 32 bytes
4
H'1000 0000 to 64 Mbytes SRAM
H'13FF FFFF
Burst ROM
8, 16, 32*²
8, 16, 32*²
8/16/32 bits
and 32 bytes
MPX
32*²
Byte control SRAM 16, 32*²
(DDR-SDRAM*⁴)
32
(PCI*⁴)
32
5
H'1400 0000 to 64 Mbytes SRAM
H'17FF FFFF
Burst ROM
8, 16, 32*²
8, 16, 32*²
8/16/32 bits
and 32 bytes
MPX
32*²
PCMCIA
8, 16*²*⁵
(DDR-SDRAM*⁴)
32
6
H'1800 0000 to 64 Mbytes SRAM
H'1BFF FFFF
Burst ROM
8, 16, 32*²
8, 16, 32*²
8/16/32 bits
and 32 bytes
MPX
32*²
PCMCIA
8, 16*²*⁵
7*⁶
H'1C00 0000 to 64 Mbytes 
H'1FFF FFFF

—
Notes: 1. The memory bus width is specified by external pins.
2. The memory bus width is specified by the register.
3. Area 3 is used specifically for the DDR-SDRAM. For details, see section 12, DDR-
SDRAM Interface (DDRIF).
4. These areas can be used for the DDR-SDRAM or PCI by setting MMSELR. For details,
see section 12, DDR-SDRAM Interface (DDRIF) or see section 13, PCI Controller
(PCIC).
5. With the PCMCIA interface, the bus width is either 8 bits or 16 bits.
6. If a reserved area is accessed, operation cannot be guaranteed.
7. If 8 or 16 bytes access transfer by another LSI internal bus master module is being
executed, the LBSC is executing two or four times 32-bit access individually.
Rev. 1.00 Oct. 01, 2007 Page 326 of 1956
REJ09B0256-0100