SH7763 Datasheet, PDF (1686/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 37 LCD Controller (LCDC)
Bit Bit Name
Initial Value R/W Description
7 to 1 
All 0
R
Reserved.
These bits are always read as 0. The write value
should always be 0.
0
UINTS
0
R/W User Specified Interrupt State
This bit is set to 1 at the time an LCDC user
specified interrupt is generated (set state). During
the user specified interrupt handling routine, this
bit should be cleared by writing 0 to it.
0: LCDC did not generate a user specified
interrupt or has been informed that the
generated user specified interrupt has
completed
1: LCDC has generated a user specified interrupt
and has not yet been notified that the generated
user specified interrupt has completed
Note:
Interrupt processing flow:
1. Interrupt signal is input
2. LDINTR is read
3. If MINTS, FINTS, VSINTS, or VEINTS is 1, a generated interrupt is memory access
interrupt, flame end interrupt, Vsync rising edge interrupt, or Vsync falling edge
interrupt. Processing for each interrupt is performed.
4. If MINTS, FINTS, VSINTS, or VEINTS is 0, a generated interrupt is not memory access
interrupt, flame end interrupt, Vsync rising edge interrupt, or Vsync falling edge
interrupt.
5. UINTS is read.
6. If UINTS is 1, a generated interrupt is a user specified interrupt. Process for user
specified interrupt is carried out.
7. If UINTS is 0, a generated interrupt is not a user specified interrupt. Other processing is
performed.
Rev. 1.00 Oct. 01, 2007 Page 1620 of 1956
REJ09B0256-0100