SH7763 Datasheet, PDF (1045/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
2. Receive Descriptor Setting
• Set RDLAR.
• Set RDFAR.
• Set RDFXR.
• Set RDFFR. When the descriptor indicated by RDFXR is the last descriptor in the descriptor
list, set H'00000001.
(3) Register Settings
The following registers should be set as necessary.
1. E-DMAC-related registers
• Set EDMR: Operating mode, etc.
• Set EESIPR: Interrupt masks
• Set TRSCER: Error masks
• Set TFTR: Transmit FIFO threshold
• Set FDR: External FIFO size
• Set RMCR: Reset method for reception activation
• Set RPADIR: Padding insertion into receive data
• Set FCFTR: Receive BSY output threshold
2. E-MAC-related registers
• Set ECMR setting: Transmission/reception specifications
• Set ECSIPR setting: Interrupt masks
• Set MAHR: MAC address
• Set MALR: MAC address
• Set RFLR: Maximum receive frame length
• Set PIPR: ET_PHY_INT pin polarity
• Set APR: TIME parameter value of an automatic pause frame
• Set MPR: TIME parameter value of a manual PAUSE frame
• Set TPAUSER: Upper limit of automatic PAUSE frame retransmission
• Set GECMR: Transfer speed
• Set BCULR: Upper limit of burst cycles
Rev. 1.00 Oct. 01, 2007 Page 979 of 1956
REJ09B0256-0100