SH7763 Datasheet, PDF (330/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value
16
NMIFL 0
15 to 0 —
All 0
R/W Description
R/W NMI Interrupt Request Signal Detection
Indicates whether an NMI interrupt request signal has
been detected. This bit is automatically set to 1 when
the INTC detects an NMI interrupt request. Write 0 to
clear the bit. Writing 1 is ignored.
[When reading]
1: NMI is detected
0: NMI is not detected
[When writing]
0: The NMI flag is cleared
1: Writing 1 is ignored
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9.3.12 User Interrupt Mask Level Register (USERIMASK)
USERIMASK is a 32-bit readable and writable with conditions register that sets the acceptable
interrupt level. When addresses in area 7 are accessed using the MMU address translation
function, USERIMASK can be accessed in user mode. Since only USERIMASK is allocated in
the 64-Kbyte page (other INTC registers are allocated to a different area), it can be set to be
accessed in user mode.
Interrupts whose priority levels are lower than the level set in the UIMASK bit are masked. If the
value of H'F is set to the UIMASK bit, all interrupts other than the NMI are masked.
Interrupts whose priority levels are higher than the level set in the UIMASK bit are accepted under
the following conditions:
• The corresponding interrupt mask bit in the interrupt mask register is cleared to 0 (the interrupt
is enabled).
• The priority level set in the IMASK bit in SR is lower than that of the interrupt.
Even if interrupts are accepted, the UIMASK value is not changed.
USERIMASK is initialized to H'0000 0000 (all interrupts are enabled) when returning from a
power-on reset or a manual reset.
Rev. 1.00 Oct. 01, 2007 Page 264 of 1956
REJ09B0256-0100