SH7763 Datasheet, PDF (704/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 Clock Pulse Generator (CPG)
16.4 Register Descriptions
Table 16.3 shows the CPG register configuration. Table 16.4 shows the register states in each
operating mode.
Table 16.3 Register Configuration
Register Name
Abbrevia-
Area P4
tion
R/W Address
Area 7
Address
Access
Size
Frequency control register FRQCR
R
H'FFC8 0000 H'1FC8 0000 32
PLL control register
PLLCR
R/W H'FFC8 0024 H'1FC8 0024 32
Table 16.4 Register States in Each Operating Mode
Register Name
Frequency control register
PLL control register
Abbrevia- Power-On Manual
tion
Reset
Reset
FRQCR H'1013 0035 Retained
PLLCR H'0000 0001 Retained
Standby
Retained
Retained
Sleep
Retained
Retained
Rev. 1.00 Oct. 01, 2007 Page 638 of 1956
REJ09B0256-0100