SH7763 Datasheet, PDF (343/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Initial
Bit
Bit Name Value
13
HAC
1
12
CMT
1
11 to 9 —
All 1
8
DMAC 1
7
H-UDI 1
6
—
1
5
WDT
1
4
SCIF1 1
3
SCIF0 1
2
RTC
1
1
TMU1
1
0
TMU0
1
Section 9 Interrupt Controller (INTC)
R/W Function
Description
R/W Masks HAC interrupts
Masks interrupts for
R/W Masks CMT interrupts
each peripheral
module.
R
These bits are always read as 1.
The write value should always be
[When writing]
1.
0: Invalid
R/W Masks DMAC interrupts
1: Interrupts are
R/W Masks H-UDI interrupts
masked
[When reading]
R
This bit is always read as 1. The
write value should always be 1. ^{0: No mask setting}
R/W Masks WDT interrupts
1: Mask setting
R/W Masks SCIF1 interrupts
R/W Masks SCIF0 interrupts
R/W Masks RTC interrupts
R/W Masks TMU1 interrupts
R/W Masks TMU0 interrupts
9.3.19 Interrupt Mask Register 1 (INT2MSKR1)
INT2MSKR1 is a 32-bit readable/writable register that sets masking for each source indicated in
the interrupt source register. Interrupts whose corresponding bits in INT2MSKR1 are set to 1 are
not notified to the CPU.
INT2MSK1 is initialized to H'FFFF FFFF (mask state) by a reset.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−−
−
−
−
− − ^SCIF2 USBF
− − ^{STIF1 STIF0}
− ^USBH
GETH
ER
Initial value:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R R R R R R R/W R/W R R R/W R/W R R R/W R/W
Bit:
Initial value:
R/W:
15 14
PCC _−
1
1
R/W R
13 12 11 10 9
8
7
6
− − ^{ADC TPU SIM SIOF2 SIOF1 LCDC}
1
1
1
1
1
1
1
1
R R/W R/W R/W R/W R/W R/W R
Note: * This bit is reserved in the R5S77631.
5
IIC1
1
R/W
4
IIC0
1
R/W
3
2
SSI3 SSI2
1
1
R/W R/W
1
0
SSI1
SECU
RITY*
1
1
R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 277 of 1956
REJ09B0256-0100