SH7763 Datasheet, PDF (115/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 2 Programming Model
Initial
Bit
Bit Name Value R/W _Description
17 to 12 Cause
All 0 R/W FPU Exception Cause Field
11 to 7 Enable (EN) All 0
6 to 2 Flag
All 0
R/W ^{FPU Exception Enable Field}
R/W ^{FPU Exception Flag Field}
Each time an FPU operation instruction is executed,
the FPU exception cause field is cleared to 0. When an
FPU exception occurs, the bits corresponding to FPU
exception cause field and flag field are set to 1. The
FPU exception flag field remains set to 1 until it is
cleared to 0 by software.
For bit allocations of each field, see table 2.2.
1, 0
RM
01
R/W Rounding Mode
These bits select the rounding mode.
00: Round to Nearest
01: Round to Zero
10: Reserved
11: Reserved
Rev. 1.00 Oct. 01, 2007 Page 49 of 1956
REJ09B0256-0100