SH7763 Datasheet, PDF (1163/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
Figure 27.8 shows a sample SCIF initialization flowchart.
Start of initialization
Clear TE and RE bits in
SCSCR to 0
Set TFCL and RFCL
bits in SCFCR to 1
Set CKE1 and CKE0 bits
in SCSCR (leaving TE, RE, TIE, [1]
and RIE bits cleared to 0)
Set data transfer format
in SCSMR
[2]
Set value in SCBRR
[3]
Wait
No
1-bit interval elapsed?
Yes
Set RTRG1-0, TTRG1-0 bits, and
MCE in SCFCR, and clear TFCL
and RFCL bits to 0
Set TE and RE bits in
SCSCR to 1, and set TIE, RIE, [4]
and REIE bits
[1] Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
[2] Set the data transfer format in
SCSMR.
[3] Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits.
Setting the TE and RE bits enables
the SCIF_TXD and SCIF_RXD pins
to be used. When transmitting, the
SCIF will go to the mark state;
when receiving, it will go to the idle
state, waiting for a start bit.
End of initialization
Figure 27.8 Sample SCIF Initialization Flowchart
Rev. 1.00 Oct. 01, 2007 Page 1097 of 1956
REJ09B0256-0100