SH7763 Datasheet, PDF (717/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 Watchdog Timer and Reset (WDT)
Bit
5
4
3
2 to 0
Initial
Bit Name Value R/W
RSTS
0
R/W
WOVF
0
R/W
IOVF
0
R/W

R
All 0
Description
Reset Select
Specifies the kind of reset to be performed when
WDTCNT overflows in watchdog timer mode. This
setting is ignored in interval timer mode.
0: Power-on reset
1: Manual reset
Watchdog Timer Overflow Flag
Indicates that WDTCNT has overflowed in watchdog
timer mode. This flag is not set in interval timer mode.
0: An overflow has not occurred
1: An overflow on WDTCNT has occurred
Interval Timer Overflow Flag
Indicates that WDTCNT has overflowed in interval
timer mode. This flag is not set in watchdog timer
mode.
0: An overflow has not occurred
1: An overflow on WDTCNT has occurred
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 651 of 1956
REJ09B0256-0100