SH7763 Datasheet, PDF (1265/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
29.3.4 Transmit Data Register (SITDR)
SITDR is a 32-bit write-only register that specifies the SIOF operating status.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SITDL[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: W W W W W W W W W W W W W W W W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SITDR[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: W W W W W W W W W W W W W W W W
Initial
Bit
Bit Name Value R/W
31 to 16 SITDL[15:0] Undefined W
15 to 0 SITDR[15:0] Undefined W
Description
Left-Channel Transmit Data
Specify data to be output from the SIOF_TXD pin as
left-channel data. The position of the left-channel data
in the transmit frame is specified by the TDLA bit in
SITDAR.
• These bits are valid only when the TDLE bit in
SITDAR is set to 1.
Right-Channel Transmit Data
Specify data to be output from the SIOF_TXD pin as
right-channel data. The position of the right-channel
data in the transmit frame is specified by the TDRA bit
in SITDAR.
• These bits are valid only when the TDRE bit and
TLREP bit in SITDAR are set to 1 and cleared to 0,
respectively.
Rev. 1.00 Oct. 01, 2007 Page 1199 of 1956
REJ09B0256-0100