SH7763 Datasheet, PDF (1366/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
31.3.6 Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD)
RSPR0 to RSPR16 are 8-bit command response registers. RSPRD is a 5-bit data response register.
The number of command response bytes differs according to the command. The number of
command response bytes can be specified through RSPTYR in the MMCIF. The command
response is shifted-in from the bit 0 in RSPR16, and shifted to the number of command response
bytes × 8 bits. Table 31.6 summarizes the correspondence between the number of command
response bytes and valid RSPR registers.
Table 31.6 Correspondence between Command Response Byte Number and RSPR
RSPR registers
RSPR0
RSPR1
RSPR2
RSPR3
RSPR4
RSPR5
RSPR6
RSPR7
RSPR8
RSPR9
RSPR10
RSPR11
RSPR12
RSPR13
RSPR14
RSPR15
RSPR16
MMC Mode Response
6 bytes
(R1, R1b, R3, R4, R5)
17 bytes
(R2)

1st byte

2nd byte

3rd byte

4th byte

5th byte

6th byte

7th byte

8th byte

9th byte

10th byte

11th byte
1st byte
12th byte
2nd byte
13th byte
3rd byte
14th byte
4th byte
15th byte
5th byte
16th byte
6th byte
17th byte
RSPR0 to RSPR16 are simple shift registers with the initial value H'00. A command response that
has been shifted in is not automatically cleared, and it is continuously shifted until it is shifted out
from bit 7 in RSPR0. To clear unnecessary bytes to H'00, write an arbitrary value to each RSPR.
Rev. 1.00 Oct. 01, 2007 Page 1300 of 1956
REJ09B0256-0100