SH7763 Datasheet, PDF (730/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 Watchdog Timer and Reset (WDT)
17.5.3 Manual Reset by Watchdog Timer Overflow
The manual reset time (watchdog timer manual reset holding time) by the watchdog timer
overflowed is equal to or more than 3774 clock cycles of the EXTAL pin input clock.
The transition time from watchdog timer overflowed to manual reset state (watchdog timer reset
setup time) is 1 clock cycle of the EXTAL input and thereafter equal to or more than 5 clock
cycles of the peripheral clock (Pck0).
The STATUS [1:0] pins output timing that indicates the reset state or a normal operation is
asynchronous with both the EXTAL pin input clock and the CLKOUT pin input clock because the
STATUS [1:0] pins output timing is synchronous with the peripheral clock (Pck0).
(1) Manual Reset by Watchdog timer Overflowed in Normal Operation
EXTAL
input
CLKOUT
output
WDT overflow
signal
MRESETOUT
output
STATUS[1:0]
output
HH (reset)
LL (normal)
WDT reset
stabilization time
Manual reset
holding time
Figure 17.8 STATUS Output by Watchdog timer overflow Manual Reset
during Normal Operation
Rev. 1.00 Oct. 01, 2007 Page 664 of 1956
REJ09B0256-0100