SH7763 Datasheet, PDF (1324/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 SIM Card Module (SIM)
Initial
Bit Bit Name Value R/W Description
0

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
30.3.7 Receive Shift Register (SCRSR)
SCRSR is a register that receives serial data.
The smart card interface receives serial data input from the SIM_RXD pin in order, from the LSB
or MSB, and sets it in SCRSR, converting it to parallel data. When reception of one byte of data is
completed, the data is automatically transferred to SCRDR. The CPU or DMAC cannot directly
read from or write to SCRSR.
30.3.8 Receive Data Register (SCRDR)
SCRDR is an 8-bit read-only register that stores received serial data.
When reception of one byte of serial data is completed, the smart card interface transfers the
received serial data from the receive shift register (SCRSR) to SCRDR for storage, and completes
the receive operation. Thereafter, SCRSR can receive data. In this way, SCRSR and SCRDR
constitute a double buffer, enabling continuous reception of data. SCRDR cannot be written to by
the CPU or DMAC.
Bit: 7
6
5
4
3
2
1
0
SCRD[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
7 to 0 SCRD[7:0] All 0
R
Receive Data
Store received serial data.
Rev. 1.00 Oct. 01, 2007 Page 1258 of 1956
REJ09B0256-0100