SH7763 Datasheet, PDF (1108/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
Bit
Bit Name Initial Value R/W Description
7 to 2
SCGD
All 0
R/W SCL Clock Generation Divider
When operating in master mode, the SCL
clock is generated from the internal clock using
SCGD as the ratio. The slave will also operate
on the clock generated from the internal clock
when SCL is held low to hold the bus up when
an overflow occurs. SCGD must be specified in
both master and slave modes. The formula
expressing the relationship is:
Equation 2 SCL rate calculation
SCLfreq = IICck / (20 + (SCGD * 8))
IICck: I²C internal clock frequency
Suggested settings for CDF and SCGD for
various CPU speeds and the two I²C bus
speeds are given in table 26.4.
1, 0
CDF
All 0
R/W Clock Division Factor
The internal clock used in most blocks in the
I²C module is a divided peripheral clock. The
internal I²C clock is generated from the
peripheral clock using the CDF as the division
ratio:
Equation 1 I²C internal clock frequency
calculation
IICck = Pck0 / (1 + CDF)
Pck0: Peripheral clock
The minimum time to ensure adequate setup
and hold times on the SDA line relative to the
SCL line on the bus.
The clock frequency is to ensure that the glitch
filtering will operate with glitches of up to 50 ns
as described in the fast mode I²C specification.
Note: CDF must be set so that the clock frequency (IICck) is lower than 20 MHz.
Rev. 1.00 Oct. 01, 2007 Page 1042 of 1956
REJ09B0256-0100