SH7763 Datasheet, PDF (420/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Initial
Bit
Bit Name Value R/W
14 to 12 TEDA
000
R/W
11

0
R
10 to 8 TEDB
000
R/W
7

0
R
Description
OE/WE Assert Delay A
These bits set the delay time from address output to
OE/WE assertion for the access of first half area of
PCMCIA interface.
000: No wait cycle inserted
001: 1 wait cycle inserted
010: 2 wait cycles inserted
011: 3 wait cycles inserted
100: 6 wait cycles inserted
101: 9 wait cycles inserted
110: 12 wait cycles inserted
111: 15 wait cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
OE/WE Assert Delay B
These bits set the delay time from address output to
OE/WE assertion for the access of second half area of
PCMCIA interface.
000: No wait cycle inserted
001: 1 wait cycle inserted
010: 2 wait cycles inserted
011: 3 wait cycles inserted
100: 6 wait cycles inserted
101: 9 wait cycles inserted
110: 12 wait cycles inserted
111: 15 wait cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 354 of 1956
REJ09B0256-0100