SH7763 Datasheet, PDF (436/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
When software wait insertion is specified by CSnWCR, the external wait input signal (RDY) is
also sampled. The RDY signal sampling timing is shown in figure 11.9, where a single wait cycle
is specified as a software wait. The RDY signal is sampled at the transition from the Tw state to
the T2 state. Therefore, the assertion of the RDY signal has no effect in the T1 cycle or in the first
Tw cycle. The RDY signal is sampled on the rising edge of the clock.
CLKOUT
A25 to A0
CSn
RDWR
RD
(read)
D31 to D0
(read)
WEn
(Write)
D31 to D0
(Write)
BS
T₁
T_w
T_we
T₂
RDY
DACKn
(DA)
DA: Dual address DMA
Figure 11.9 SRAM Interface Wait Cycle Timing (Wait Cycle Insertion by RDY Signal)
Rev. 1.00 Oct. 01, 2007 Page 370 of 1956
REJ09B0256-0100