SH7763 Datasheet, PDF (387/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figure 11.1 shows a block diagram of the LBSC.
Section 11 Local Bus State Controller (LBSC)
RDY
CS0 to CS2
CS4 to CS6
CE2A, CE2B
CE1A, CE1B
A0 to A25
BS
RD
RD/FRAME
RDWR
WE3/IOWR
WE2/IORD
WE1/WE
WE0/PCC_REG
BACK
D0 to D31
IOIS16
BREQ
MD3 to MD5
Wait
control
unit
Area
control
unit
Memory
control
unit
CSnWCR
CSnBCR
BCR
CSnPCR
[Legned]
BCR
CSnBCR
CSnPCR
CSnWCR
Bus Control Register
Bus Control Register (n = 0 to 2, 4 to 6)
CSn Bus Control Register (n = 5 to 6)
CSn Wat Control Register (n = 0 to 2, 4 to 6)
Bus
interface
LBSC
Figure 11.1 LBSC Block Diagram
Rev. 1.00 Oct. 01, 2007 Page 321 of 1956
REJ09B0256-0100