SH7763 Datasheet, PDF (1251/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
Section 29 Serial I/O with FIFO (SIOF)
This LSI includes a clock-synchronized serial I/O module with FIFO (SIOF) that comprises three
channels.
29.1 Features
• Three channels of serial I/O
• Serial transfer
16-stage 32-bit FIFOs (transmission and reception are independent of each other)
Supports 8-bit data/16-bit data/16-bit stereo audio input/output
MSB first for data transmission
Supports a maximum of 48-kHz sampling rate
Synchronization by either frame synchronization pulse or left/right channel switch
Supports CODEC control data interface
Connectable to linear, audio, or A-Law or µ-Law CODEC chip
Supports both master and slave modes
• Serial clock
An external pin input or peripheral clock (Pck0) can be selected as the clock source.
• Interrupts: One type
• DMA transfer
Supports DMA transfer by a transfer request for transmission and reception
Rev. 1.00 Oct. 01, 2007 Page 1185 of 1956
REJ09B0256-0100