SH7763 Datasheet, PDF (675/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
5. Hereafter, steps 2 and 4 are repeated until the DME or DE bit is cleared to 0, or an NMI
interrupt is generated. Note that if the HE bit is not cleared in the procedure 3 or if the TE bit is
not cleared in the procedure 4, then the transfer is stopped according to the condition of both
the HE and the TE bits are set to 1.
As explained above, a repeat mode transfer enables sequential voice compression by changing
buffer for storing data received consequentially and a data buffer for processing signals
alternately.
14.4.6 Reload Mode Transfer
In a reload mode transfer, according to the settings of bits RPT[2:0] in CHCR, the value set in
SARB/DARB is set to SAR/DAR and the value of bits TCRB[23:16] is set in bits TCRB[7:0] at
each transfer set in the bits TCRB[7:0], and the transfer is repeated until TCR becomes 0 without
specifying the transfer settings again. A reload mode transfer is effective when repeating data
transfer with specific area. Figure 14.12 shows the operation of reload mode transfer.
DMAC
Transfer request
Reload controller
Bits RPT[2:0]
CHCR
TCR
Transfer counter
TCRB
Reload signal
Reload counter
SAR/DAR
SARB/DARB
Figure 14.12 Reload Mode Transfer
When a reload mode transfer is executed, TCRB is used as a reload counter. Set TCRB according
to section 14.3.6, DMA Transfer Count Registers (TCRB0 to TCRB3).
Rev. 1.00 Oct. 01, 2007 Page 609 of 1956
REJ09B0256-0100