SH7763 Datasheet, PDF (504/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
12.6 DDRIF Basic Timing
Figures 12.5 to 12.14 show examples of basic DDRIF timing.
In every figure, the DDR-SDRAM is idle at T0.
The various timings should be set in the STR register within the range specified by the DDR-
SDRAM used.
Note that the DDRIF only supports 2.5-cycle CAS latency (CL).
(MCLK)
MCLK
CKE
Command
MA9-0
MA13-11
MA10
BA1-0
MCS
MRAS
MCAS
MWE
MDQS
MDA
MDQM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
ACT
Row
READ
t_RCD (SRCD = 1)
Col 0
Row
Bank
Bank
PRE
Bank
Hi-Z
CL = 2.5
Hi-Z
D0 D1
Figure 12.5 Basic DDRIF Timing (1 Burst Read: 1, 2, 4, or 8 Bytes; Without Auto-
Precharge)
Rev. 1.00 Oct. 01, 2007 Page 438 of 1956
REJ09B0256-0100