SH7763 Datasheet, PDF (1172/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
Start of initialization
Clear TE and RE bits
in SCSCR to 0
[1]
Set TFCL and RFCL bits
in SCFCR to 1 to clear
the FIFO buffer
After reading BRK, DR,
and ER flags in SCFSR,
write 0 to clear them
Set CKE1 and CKE0 bits
in SCSCR (leaving TE, RE, TIE, _[2]
and RIE bits cleared to 0)
Set data transfer format
[3]
in SCSMR
Set value in SCBRR
[4]
Wait
No
1-bit interval elapsed?
Yes
Set RTRG1-0 and TTRG1-0 bits
in SCFCR, and clear TFCL
and RFCL bits to 0
Set external pins to be used
(SCIF_SCK, SCIF_TXD,
[5]
and SCIF_RXD)
Set TE and RE bits in SCSCR
to 1, and set TIE, RIE,
[6]
and REIE bits
[1] Leave the TE and RE bits cleared
to 0 until the initialization almost
ends. Be sure to clear the TIE,
RIE, TE, and RE bits to 0.
[2] Set the CKE1 and CKE0 bits.
[3] Set the data transfer format in
SCSMR.
[4] Write a value corresponding to
the bit rate into SCBRR. This
is not necessary if an external
clock is used. Wait at least one
bit interval after this write before
moving to the next step.
[5] Set the external pins to be used.
Set SCIF_RXD input for reception and
SCIF_TXD output for transmission.
The input/output of the SCIF_SCK pin
must match the setting of the
CKE1 and CKE0 bits.
[6] Set the TE or RE bit in SCSCR
to 1. Also set the TIE, RIE, and
REIE bits to enable the SCIF_TXD,
SCIF_RXD, and SCIF_SCK pins to
be used. When transmitting, the
SCIF_TXD pin will go to the mark
state. When receiving in clocked
synchronous mode with the
synchronization clock output (clock
master) selected, a clock starts to
be output from the SCIF_SCK pin
at this point.
End of initialization
Figure 27.16 Sample SCIF Initialization Flowchart
Rev. 1.00 Oct. 01, 2007 Page 1106 of 1956
REJ09B0256-0100