SH7763 Datasheet, PDF (1573/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.2 Interrupt Flag Register 1 (IFR1)
IFR1 is an interrupt flag register for VBUS and EP3. When each flag is set to 1 and an interrupt is
enabled in the corresponding bit of IER1, an interrupt request (USBFI0 or USBFI1) specified by
the corresponding bit in ISR1 is issued to INTC.
Clearing the flag is performed by writing 0. Writing 1 is not valid and nothing is changed. To clear
bits, access the register so that 0 should be written only to the bits for the interrupt sources to be
cleared and that 1 should be written to the other bits. Do not use a bit field declaration of the C
language to clear bits.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
VBUS EP3
MN TR
EP3
TS
VBUSF
Initial value: — — — — — — — — 0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R/W R/W R/W
Bit
Bit Name Initial Value
31 to 8 
Undefined
7 to 4 
All 0
3
VBUS MN 0
R/W Description
R Reserved
These bits are always read as undefined value. Write
value should always be 0.
R Reserved
These bits are always read as 0. The write value
should always be 0.
R USB Connection Status
Status bit to monitor the USBF_VBUS pin state.
Reflects the state of the USBF_VBUS pin.
0: Disconnected
1: Connected
Rev. 1.00 Oct. 01, 2007 Page 1507 of 1956
REJ09B0256-0100