SH7763 Datasheet, PDF (1787/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 40 General Purpose I/O (GPIO)
40.2.16 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores port A data.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
PA6DT
0
R/W Each of these bits stores output data for the
5
PA5DT
0
R/W ^{corresponding pin that is used as a general output port.}
If the port is read, the value of the corresponding bit in
4
PA4DT
0
R/W _{this register will be read for a pin configured as a}
3
PA3DT
0
R/W ^{general output port, while the state of the}
corresponding pin will be read for a pin configured as a
2
PA2DT
0
R/W _{general input port.}
1
PA1DT
0
R/W
0
PA0DT
0
R/W
Rev. 1.00 Oct. 01, 2007 Page 1721 of 1956
REJ09B0256-0100