SH7763 Datasheet, PDF (395/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
11.3.3 Data Alignment
This LSI supports big endian and little endian as data alignment. Data alignment is determined by
the level of the external pin (MD5) at a power-on reset.
Table 11.4 Correspondence between External Pin (MD5) and Endian
MD5
Low
High
Data Alignment
Big endian
Little endian
11.3.4 PCMCIA Support
This LSI supports the PCMCIA interface specifications for areas 5 and 6 in the external memory
space.
The IC memory card interface and I/O card interface prescribed in JEIDA specifications version
4.2 (PCMCIA2.1) are supported.
Both the IC memory card interface and the I/O card interface are supported in areas 5 and 6 in the
external memory space.
The PCMCIA interface is only supported in little endian mode.
Table 11.5 PCMCIA Interface Features
Item
Access
Data bus
Memory type
Common memory capacity
Attribute memory capacity
Others
Features
Random access
8/16 bits
Masked ROM, OTPROM, EPROM, flash memory, SRAM
Maximum 64 Mbytes
Maximum 64 Mbytes
Dynamic bus sizing for I/O bus width
Rev. 1.00 Oct. 01, 2007 Page 329 of 1956
REJ09B0256-0100