SH7763 Datasheet, PDF (1186/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
• Clocked synchronous serial communication mode
Serial data communication is synchronized with a clock. Serial data communication can be
carried out with other LSIs that have a synchronous communication function.
There is a single serial data communication format.
 Data length: 8 bits
 Receive error detection: Overrun errors
• Full-duplex communication capability
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling continuous
serial data transmission and reception.
• The LSB is transmitted and received first (LSB first).
• On-chip baud rate generator allows any bit rate to be selected.
• Choice of clock source: internal clock from the baud rate generator based on the peripheral
clock (Pck0) or external clock from the SCIF2_SCK pin
• Four interrupt sources
There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full,
and receive-error—that can issue requests independently.
• The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA
transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
• The amount of data in the transmit/receive FIFO registers, and the number of receive errors in
the receive data in the receive FIFO register, can be ascertained.
• In asynchronous mode, a timeout error (DR) can be detected during reception.
Rev. 1.00 Oct. 01, 2007 Page 1120 of 1956
REJ09B0256-0100