SH7763 Datasheet, PDF (1849/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 41 User Break Controller (UBC)
6. While the BL bit in the SR register is 1, no break requests are accepted. However, whether or
not the condition has been satisfied is determined. When the condition is determined to be
satisfied, the corresponding condition match flag is set.
7. If the sequential break conditions are set, the condition match flag is set every time the match
conditions are satisfied for each channel. When the conditions have been satisfied for the first
channel in the sequence but not for the second channel in the sequence, clear the condition
match flag for the first channel in the sequence in order to release the first channel in the
sequence from the match state.
Rev. 1.00 Oct. 01, 2007 Page 1783 of 1956
REJ09B0256-0100