SH7763 Datasheet, PDF (1089/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
(3) Strobe Transmission
(a) Strobe Transmission Interface
• Timing chart
Figure 25.6 shows the timing of the strobe transmission interface. Data is updated
simultaneously with the falling edge of the ST_STRB pin.
ST_STRB (output)
ST_START (output)
ST_VALID (output)
ST_REQ (input)
ST_D7 to ST_D0
(output)
Figure 25.6 Strobe Transmission Timing
• Active level setting for ST_STRB, ST_START, ST_VALID, and ST_REQ pins
The active levels of the ST_STRB, ST_START, ST_VALID, and ST_REQ pins can be set by
the STRB, STAT, VLD, and REQ bits in STIMDR, respectively.
• Selection of ST_REQ pin usage
When strobe transmission is selected, the ST_REQ pin always functions as an input pin
regardless of the REQEN bit setting in STIMDR.
(b) Transmit Packet Length
The transmit packet length can be selected from 188 and 192 bytes.
Since the packet length is handled as 192 bytes in external memory, the first four bytes of a packet
are removed before transmission when the transmit packet length is set to 188 bytes. When the
transmit packet length is set to 192 bytes, external memory data is transmitted without changes.
(c) Work Area
The size of the work area in external memory can be selected from among 0, 16, 32, and 48 bytes.
Rev. 1.00 Oct. 01, 2007 Page 1023 of 1956
REJ09B0256-0100