SH7763 Datasheet, PDF (896/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.18 Residual-Bit Frame Receive Counter Register (RFCR)
RFCR is a 16-bit counter that indicates the number of frames received containing residual bits
(less than an 8-bit unit). When the value in this register reaches H'0000FFFF, count-up is halted.
This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the
TRCCM bit in ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RFC[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 16 
Initial
Value
All 0
15 to 0 RFC[15:0] All 0
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Residual-Bit Frame Receive Count
These bits indicate the number of frames received
containing residual bits.
Rev. 1.00 Oct. 01, 2007 Page 830 of 1956
REJ09B0256-0100