SH7763 Datasheet, PDF (972/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.70 E-DMAC Transmit Request Register (EDTRR)
EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC. After
writing 11 to bits TR[1:0] in this register, the E-DMAC reads the transmit descriptor at the address
specified by TDLAR. If the TACT bit of this transmit descriptor is set to 1 (valid), transmit DMA
transfer by the E-DMAC starts. When DMA transfer based on the first transmit descriptor is
completed, the E-DMAC reads the next transmit descriptor. If the TACT bit of that transmit
descriptor is set to 1 (valid), the E-DMAC continues transmit DMA operation. If the TACT bit of
a transmit descriptor is cleared to 0 (invalid), the E-DMAC clears bits TR[1:0] and stops transmit
DMA operation.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0














TR[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R/W R/W
Bit
31 to 2
1, 0
Initial
Bit Name Value

All 0
TR[1:0] 00
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Transmit Request
00, 01, 10: Transmission-halted state
If 00, 01, or 10 is written to these bits, the E-
DMAC stops DMA transfer of the currently
processed transmit descriptor, reads the next
transmit descriptor, and then clears these bits.
(Write-back is completed for the valid transmit
descriptors that have been detected up till then.)
The E-DMAC clears these bits when transmit
descriptor empty occurs, or transmission of a
transmit descriptor has completed. (Write-back
is completed for the valid transmit descriptors
that have been detected up till then.)
11: Transmit DMA operation by E-DMAC
After writing 11 to these bits, the E-DMAC starts
reading a transmit descriptor.
Rev. 1.00 Oct. 01, 2007 Page 906 of 1956
REJ09B0256-0100