SH7763 Datasheet, PDF (743/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Power-Down Mode
Initial
Bit
Bit Name Value R/W Description
10
TMU1
0
R/W TMU1 Module Stop Bit
When set to 1, the clock supply to the TMU1 module is
halted.
0: TMU1 operates
1: Clock supply to TMU1 is halted
9
TMU0
0
R/W TMU0 Module Stop Bit
When set to 1, the clock supply to the TMU0 module is
halted.
0: TMU0 operates
1: Clock supply to TMU0 is halted
8
TPU
0
R/W TPU Module Stop Bit
When set to 1, the clock supply to the TPU module is
halted.
0: TPU operates
1: Clock supply to TPU is halted
7 to 4 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
MMC
0
R/W MMC Module Stop Bit
When set to 1, the clock supply to the MMC module is
halted.
0: MMC operates
1: Clock supply to MMC is halted
2 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note: When writing to a certain bit in MSTPCR1, read all values in MSTPCR1 first and rewrite the
certain bit, then return the renewed values back to MSTPCR1.
Rev. 1.00 Oct. 01, 2007 Page 677 of 1956
REJ09B0256-0100