SH7763 Datasheet, PDF (969/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.68 E-DMAC Start Register (EDSR)
EDSR specifies activation of the transmitting unit and receiving unit of the E-DMAC. This
register can only be written to, and the read values are invalid.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0













 ENT ENR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R W W
Bit
31 to 2
Bit Name

1
ENT
0
ENR
Initial
Value
All 0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
W E-DMAC Transmitting Unit Start
0: Stops the E-DMAC transmitting unit
1: Starts the E-DMAC transmitting unit
W E-DMAC Receiving Unit Start
0: Stops the E-DMAC receiving unit
1: Starts the E-DMAC receiving unit
Rev. 1.00 Oct. 01, 2007 Page 903 of 1956
REJ09B0256-0100