SH7763 Datasheet, PDF (547/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(25) PCI Power Management Capability Register (PCIPMC)
PCIPMCS is a 16-bit register that provides information on the capabilities of the power
management related functions. For details, refer to “PCI Bus Power Management Interface
Specification Revision 1.1 Chapter 3 PCI Power Management Interface”. This register must be set
during initializing the PCIC registers (PCICR.CFINIT = 0).
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PMCS
D2S D1S    DSI  PMEC
PMV
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
SH R/W: R R R R R R/W R/W R R R R R R/W R/W R/W R/W
PCI R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value R/W
15 to 11 PMCS
00000 SH: R
PCI: R
10
D2S
9
D1S
0
SH: R/W
PCI: R
0
SH: R/W
PCI: R
Description
PME_SUPPORT
This 5-bit field indicates the power states in which the
function may assert PME. A value of 0b for any bit
indicates that the function is not capable of asserting
the PME signal while in that power state.
Bit11: xxxx1 - PME can be asserted from D0
Bit12: xxx1x - PME can be asserted from D1
Bit13: xx1xx - PME can be asserted from D2
Bit14: x1xxx - PME can be asserted from D3 hot
Bit15: 1xxxx - PME can be asserted from D3 cold
Note: This LSI dose not have the PME pin.
When this bit is 1, This function supports the D2
power management state. When the D2 power
management state is not supported, this bit is read as
0.
When this bit is 1, This function supports the D1
power management state. When the D1 power
management state is not supported, this bit is read as
0.
Rev. 1.00 Oct. 01, 2007 Page 481 of 1956
REJ09B0256-0100