SH7763 Datasheet, PDF (577/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(15) PCI Power Management Interrupt Mask Register (PCIPINTM)
This is the mask register for PCIPINT.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: — — — — — — — — — — — — — — — —
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
PMD PMD PMD PMD
3HM 2M 1M 0M
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R/W R/W R/W R/W
PCI R/W: — — — — — — — — — — — — — — — —
Bit
31 to 4
Bit Name

Initial
Value
All 0
R/W
SH: R
PCI: 
3
PMD3HM 0
SH: R/W
PCI: 
2
PMD2M 0
SH: R/W
PCI: 
1
PMD1M 0
SH: R/W
PCI: 
0
PMD0M 0
SH: R/W
PCI: 
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
PCI Power Management D3 Hot Status Transition
Interrupt Mask
0: PCIPINT.PM D3H disabled (masked)
1: PCIPINT.PM D3H enabled (not masked)
PCI Power Management D2 Status Transition
Interrupt Mask
0: PCIPINT.PMD2 disabled (masked)
1: PCIPINT.PMD2 enabled (not masked)
PCI Power Management D1 Status Transition
Interrupt Mask
0: PCIPINT.PMD1 disabled (masked)
1: PCIPINT.PMD1 enabled (not masked)
PCI Power Management D0 Status Transition
Interrupt Mask
0: PCIPINT.PMD0 disabled (masked)
1: PCIPINT.PMD0 enabled (not masked)
Rev. 1.00 Oct. 01, 2007 Page 511 of 1956
REJ09B0256-0100