SH7763 Datasheet, PDF (1369/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
Command sequences are controlled by the sequencers on both the MMCIF side and the MMC
card side. Normally, these operate synchronously. However, if an error occurs or a command is
aborted, these may become temporarily unsynchronized. Be careful when setting the CMDOFF bit
in OPCR, issuing the CMD12 command, or processing an error in MMC mode. A new command
sequence should be started only after the end of the command sequence on both the MMCIF and
card sides is confirmed.
Bit: 7
6
5
4
3
2
1
0
— — — — — — — START
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R/W
Bit
7 to 1
0
Initial
Bit Name Value R/W
—
All 0 R
START
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Starts command or Stop Tran transmission when 1 is
written. This bit is cleared by hardware.
Rev. 1.00 Oct. 01, 2007 Page 1303 of 1956
REJ09B0256-0100