SH7763 Datasheet, PDF (476/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
Figure 12.1 shows a block diagram of the DDRIF.
LCDC
LCDC
interface
(LCDIF)
SuperHyway bus
interface
(SHIF)
DDRIF
Arbiter
(ARBT)
From CPG
DLL
DDR-SDRAM
controller
(DDRC)
DDR
I/O
M_CLK0
M_CLK1
M_BKPRST
M_CKE
M_CS
M_RAS
M_CAS
M_WE
M_BA1, M_BA0
M_A13 to
M_A 0
M_DQM3 to
M_DQM0
M_DQS3 to
M_DQS0
M_D31 to
M_D0
M_VREF
Figure 12.1 DDRIF Block Diagram
• The SuperHyway bus interface (SHIF) is an interface between the CPU and SDRAM. The
SuperHyway bus protocol is used for interface. The bus width is 64 bits and the maximum
operating frequency is 133 MHz.
• The LCDC interface (LCDIF) is an interface with the LCDC. The bus width is 32 bits and the
maximum operating frequency is 66 MHz.
• The arbiter (ARBT) arbitrates SHIF that accesses the DDR-SDRAM and LCDIF requests
among the requests from the abovementioned interfaces.
• The DDR-SDRAM controller (DDRC) controls read/write accesses to the DDR-SDRAM.
Commands are issued and read data is received according to the specified timing of the DDR-
SDRAM. Arbitration between the interfaces described above is performed with the priority
order determination defined separately. The I/O block that drives the DDR-SDRAM interface
signal and the register block related to the control of the DDR-SDRAM are included.
Rev. 1.00 Oct. 01, 2007 Page 410 of 1956
REJ09B0256-0100