SH7763 Datasheet, PDF (738/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Power-Down Mode
18.3.2 Module Stop Register 0 (MSTPCR0)
MSTPCR0 is a 32-bit readable/writable register that can individually start or stop the module
assigned to each bit.
MSTPCR0 can be accessed only in longwords.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
LCDC — — — — — — — — — — — — — — —
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R R R R R R R R R R R R
Bit
31 to 16
Bit Name

Initial
Value
All 0
15
LCDC
0
14 to 0 
All 0
R/W
R
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
LCDC Module Stop Bit
When set to 1, the clock supply to the LCDC module is
halted.
0: LCDC operates
1: Clock supply to LCDC is halted
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 672 of 1956
REJ09B0256-0100